As the integration density of semiconductor field effect transistor (FET) devices continues to increase, with conventional configurations this may cause problems such as short channel effects and drain induced barrier lowering (DIBL) as smaller and smaller transistors are integrated in bulk devices. Another problem that may arise with bulk integration is achieving a desired sub-threshold slope (SS), for example.
Various semiconductor configurations have been developed to address challenges associated with increasing integration densities. One example is set forth in U.S. Pat. Pub. No. 2011/0281410 to Liu et al. This reference discloses a transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel. The method includes forming a hard mask on a substrate and forming an opening in the hard mask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
U.S. Pat. No. 7,883,944 to Zhu et al. discloses a method of forming a semiconductor device that may include providing a semiconductor layer including raised source and raised drain regions that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain regions overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.
Despite the existence of such configurations, further enhancements may be desirable to more effectively address semiconductor device integration issues such as SCE and DIBL, for example.